Published on

Understanding TSV Technology in One Article


From HBM memory to 3D NAND chips to CoWoS, there are many chips on the hardware market that are built with what is known in English as TSVs, an acronym that means "Through Silicon Vias" and translates to via the fact that the silicon passes vertically through the chips and allows for perpendicular interworking between them. In this article we will tell you what they are, how they work and what they are used for.

In the first month of 2000, Professor Sergey Savastiou of Santa Clara University published an article in the journal Solid State Technology called "Moore's Law - the Z dimension ". The last chapter of the article is titled Through-Silicon Vias, which is the first time the term Through-Silicon Via has been used in the world. The timing of this article also seems to indicate that TSV is destined to have a remarkable run in the new millennium.

Schematic diagram of TSV

TSV, which stands for Through-Silicon Via, is a vertical electrical interconnect across a silicon substrate.

If Wire bonding and Flip-Chip Bumping provide electrical interconnections to the outside of the chip, and RDL provides horizontal interconnections inside the chip, TSV provides vertical interconnections inside the wafer. As the only vertical electrical interconnect technology, TSV is one of the most central technologies for advanced semiconductor packaging.

In the mid-1990s, a major event occurred in the semiconductor industry: IBM replaced sputtered aluminium with the copper electroplated damascene process for transistor interconnects in integrated circuits. This made copper plating a standard process in the semiconductor industry, which made copper plating for TSV microvia metallisation filling even more logical. (Recommendation: Summary of all advanced packaging companies in China (as of October 2023)) At this point, the two core technologies of modern TSVs, deep silicon etching and electroplating, have emerged.

TSV not only gives the chip the ability to integrate in the longitudinal dimension, but it also has the shortest electrical transmission path and excellent interference immunity. As Moore's Law slowly comes to an end, the miniaturisation of semiconductor devices relies more and more on advanced packages integrating TSVs, which are extremely important for devices such as CMOS Image Sensors (CIS), High Bandwidth Memory (HBM), and Silicon interposers. are extremely important. Because of the light-sensitive surface, the electrical signals of the CIS chip must be led out from the back, so the TSV becomes the essential electrical interconnection structure. HBM is a memory chip based on multi-layer stacking, and nowadays HBM can achieve 12-layer stacking, and I believe that 16-layer or more layer stacking will be realised in the near future, which is, of course, indispensable for the interconnection of the TSV. Silicon interposer can integrate many kinds of chips, such as CPU, memory, ASIC, etc. into a key component of the package module, and its vertical interconnection also needs TSV. In fact, Yole development consulting company in France has done a study and found that TSV can be applied to almost any chip package and any type of advanced packaging, including LED, memory, ASIC, etc. advanced packages, including LEDs, MEMS, and so on. (Recommended: Exploring Advanced Packaging Technologies: The Road to Innovation Beyond Traditional Packaging (with PPT))


It is because of the importance of TSV that major foundries and OSTA companies are constantly investing in the research and development of TSV technology. The focus of R&D at this stage is how to ensure that plating deposition occurs primarily within the TSV vias rather than on the wafer surface. If no measures are taken, the rate of metal deposition on the silicon surface during plating will be much faster than inside the TSV vias. The current solution to this problem is to add inhibitors and accelerators to the plating solution to inhibit metal deposition on the wafer surface and accelerate deposition within the TSV vias, respectively. (Recommended reading: 078BOOK | "Advanced Packaging Materials" 591-page PDF e-book) In order to obtain the perfect filler effect and high enough yield, the major Foundry and OSTA companies have done a lot of research to obtain the best plating parameters, such as current, temperature, wafer and electrode position relative to the concentration of additives and so on. Major semiconductor equipment companies have also begun to introduce special semiconductor equipment for TSV plating.


According to the above equation, by recording the interference pattern and performing Fourier cosine transformation through the basic equation of Fourier Transform Spectroscopy, the intensity at any wave number can be obtained. However, this transformation process is highly complex and cumbersome, requiring the use of computers. In other words, Fourier Transform Infrared Spectroscopy (FTIR) became practical only after the emergence and development of computers, as they are essential for carrying out the required mathematical computations.

In the hardware world, it is often talked about in terms related to speed, i.e., whether it is the bandwidth of the memory, the clock cycles of the processor, the number of times per second that the processor performs a certain type of computation, etc., but we seldom ask ourselves how these chips are communicating with each other and whether this is important.

What is silicon or TSV pathway?

If we look at most motherboards, we can see two things: first, most of the connections between the chips are horizontal, which means that the paths on the board that send signals between the chips communicate horizontally.



Then there is the case of the CPUs, which are placed on top of inserters we call sockets, and the processors are connected vertically on these inserters.



But usually, 99% of the time, we observe chips that are not usually connected vertically to each other, despite the fact that chip and processor design is moving in this direction and there are already examples of this type on the market. But how to interconnect two or more chips vertically?



Well, it is done through so-called silicon channels, which run vertically through different chips or layers of the same chip that make up the stack, which is why they are called "through" silicon channels, because they actually pass through.

Applications and advantages of using TSVs

One of the applications of TSVs is that they allow complex processors consisting of different parts to be separated on several different chips, with the following additional advantages: Vertical connectivity allows for a larger number of connections, which helps to achieve a larger bandwidth without the need for additional bandwidth. Very high clock frequencies increase power consumption during data transmission.

For example, in the future, we will see that the last level of cache for CPUs and GPUs will not be on the chip; they will have the same bandwidth but several times the storage capacity, which will greatly improve performance. We also have examples of Intel Foveros using FSV to communicate between the two parts of the Lakefield SoC, i.e. the compute chip with the base chip where the system I/O is located.


Apple's M1 ULTRA processor, introduced on 9 March 2022, is a burst of performance in which multiple CPUs are integrated using a Silicon interposer with TSVs. Nowadays, TSV is increasingly indispensable for AI/AR/VR sensors, image sensors, stacked memory chips, and high-performance processors, and TSV, a lesser-known technology, is having a profound impact on the way people live and work at the bottom of the hardware hierarchy. More than half a century ago, in the autumn, Schottky's idea of punching holes in a silicon wafer ultimately ushered mankind into the age of artificial intelligence.