What are the differences between Scan and BIST in chip design and testing?

Summary

Scan Design: A methodology used to test the internal logic of a chip by inserting scan chains that allow for the shifting in and out of test patterns.

BIST (Built-In Self-Test): A technique where the chip includes additional circuitry to test itself using internally generated test patterns, reducing the need for external test equipment.

Complexity: BIST increases the complexity of chip design due to the additional circuitry required, whereas scan design primarily involves adding scan chains.

Test Equipment: Scan design typically requires expensive external test equipment (ATE), while BIST can operate independently of such equipment.

Test Coverage: BIST can achieve high fault coverage with a large number of pseudo-random patterns, while scan design uses deterministic patterns to target specific faults.

Application: BIST is often used for memory testing (MBIST) and logic testing (LBIST), while scan design is used for testing the internal logic of digital circuits. Cost: BIST can reduce overall testing costs by minimizing the need for external test equipment, but it may increase the initial design cost due to added complexity.

Figure 1:By inserting some extra hardware circuitry between logic A and logic B, it is possible to observe & control the value passed from logic A to logic B.Image source: PERCEPTIVE

Scan Design

Definition: Scan design is a DFT technique that involves adding scan chains to a chip to facilitate testing.

Methodology: It allows for the shifting in and out of test patterns to test the internal logic of the chip.

Equipment: Requires external test equipment like Automatic Test Equipment (ATE) to apply and analyze test patterns.

Fault Coverage: Uses deterministic patterns to target specific faults, such as stuck-at and transition faults.

Advantages: Provides high fault coverage and is well-suited for complex digital circuits.

Figure 2:A typical sequential circuit (before scan insertion).

BIST (Built-In Self-Test)

Definition: BIST is a technique where the chip includes additional circuitry to test itself using internally generated test patterns.

Types: Includes Logic BIST (LBIST) for logic testing and Memory BIST (MBIST) for memory testing.

Operation: Generates pseudo-random test patterns and compares the results to expected behavior.

Advantages: Reduces the need for external test equipment and can perform tests during normal operation.

Challenges: Increases the complexity of chip design and may require more die area.

Figure 3: Functional block diagram of BIST circuitry.Image source: ADI

Complexity and Cost

BIST Complexity: Increases due to the additional circuitry required for self-testing.

Scan Design Complexity: Primarily involves adding scan chains, which is less complex than BIST.

Cost Implications: BIST can reduce overall testing costs by minimizing the need for external test equipment, but it may increase the initial design cost.

Design Trade-offs: Designers must balance the complexity and cost of implementing BIST versus the benefits of reduced external testing requirements.

Figure 4: Broadcast-based multiple single input charge (BMSIC)-TPG structure.

Test Equipment

Scan Design: Requires expensive external test equipment like ATE to apply and analyze test patterns.

BIST: Operates independently of external test equipment, reducing the need for such equipment.

Cost Savings: BIST can lead to significant cost savings in testing by minimizing the reliance on external equipment.

Field Tests: BIST is useful for field tests and at-speed tests, reducing the need for ATE in these scenarios.

Test Coverage

BIST Coverage: Achieves high fault coverage with a large number of pseudo-random patterns.

Scan Design Coverage: Uses deterministic patterns to target specific faults, providing high fault coverage.

Pattern Sets: BIST uses a single pattern set to target all types of faults, while scan design may require multiple sets of patterns.

Fault Models: Scan design can target specific fault models like stuck-at, transition, and path delay faults.

Applications

Scan Design: Used for testing the internal logic of digital circuits.

BIST: Often used for memory testing (MBIST) and logic testing (LBIST).

Field Tests: BIST is useful for field tests and at-speed tests.

In-System Tests: BIST can perform tests during normal operation, making it suitable for in-system testing.

Hybrid Approaches

Combination: Some designs use a combination of both scan design and BIST to achieve comprehensive test coverage.

Hybrid Testing: Combines the benefits of deterministic ATPG patterns and pseudo-random BIST patterns.

Cost and Efficiency: Hybrid approaches can reduce test times and costs by leveraging the strengths of both techniques.

Tools: EDA vendors provide tools to reuse logic between ATPG embedded compression and logic BIST.