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Application and Case Analysis of De-Capping and De-Layering
- Authors
- Name
- Universallab
- @universallab
Introduction
Semiconductor device products mainly include capacitors, resistors, inductors, diodes, transistors, crystal oscillators, integrated circuits (ICs), and more. With the surge in the use of electronic products, failures are inevitable. Analyzing failed components to identify failure modes, analyze failure mechanisms, and determine root causes is crucial for reducing or preventing future failures, which is of great significance to the development of enterprises. The complexity of failure causes is often due to differences in working environments and usage processes, and failures are often unique and non-reproducible. Therefore, rigorous sample preparation is required before destructive analysis and testing, as proper sample preparation provides a reliable foundation for subsequent analysis. Sample preparation includes de-capping, de-layering, backside grinding, DIE extraction, sectioning, ion milling, and more. This article mainly shares the technical methods and case analysis of de-capping and de-layering.
Decap
Decap, also known as de-lidding or de-capping, refers to the partial processing of a fully packaged IC to expose the IC while preserving the integrity and functionality of the chip. This process ensures that the die, bond pads, bond wires, and even the lead frame remain undamaged, preparing the chip for subsequent failure analysis experiments and facilitating observation or other testing methods (such as FIB, EMMI). The scope of decapping includes standard packages, COB, BGA, QFP, QFN, SOT, TO, DIP, BGA, COB, ceramic, metal, and other special packaging types. Common decapping methods include chemical decapping, mechanical decapping, and laser decapping.
Chemical Decapping
In this method, the polymer resin is degraded by hot concentrated nitric acid (98%) or concentrated sulfuric acid into low-molecular compounds that are easily soluble in acetone. These low-molecular compounds are then removed by ultrasonic cleaning, exposing the surface of the chip. This method is suitable for non-silver wire plastic-encapsulated products, allowing for easy and quick removal of the plastic encapsulation while leaving the chip surface clean.
Mechanical Decapping
For metal enclosures, manual grinding is typically used for decapping. This involves grinding away the surface metal cover with sandpaper to expose the internal chip. Some devices require exposure to light, so they are encapsulated with transparent glass. For these products, the decapping process usually involves heating and using specialized tools to pry open the sealed area, separating the top and bottom parts to achieve decapping.
Laser Decapping
The IC is placed on the stage of a laser decapping machine, where the focus is aligned to the device surface using a signal light. The desired pattern is drawn, and appropriate laser energy and the number of laser passes are set. The laser is then applied to the specified area to achieve purposes such as thinning the sample, exposing the second bonding point, or reaching the substrate.
Principle and Components of a Laser Decapping Machine
The laser decapping machine primarily consists of four parts: the working area, laser source, scanning head, and imaging system. The laser decapping machine for chips uses a high-energy laser beam to evaporate, chemically react with, or burn the surface of the material being processed. This allows for the creation of permanent marks on the surface of the processed object or for thinning the sample.
Given the complexity of various devices, one or more of the aforementioned techniques are often employed to achieve optimal decapping results.
Applications
Delayering
Delayering, also known as delayer, is a technique widely used in chip production, failure analysis, and reverse engineering. Delayering techniques can be categorized into dry and wet methods. Dry delayering mainly utilizes Reactive Ion Etching (RIE) equipment or mechanical grinding to remove layers. Wet delayering involves using specific chemical solutions that react with the thin film layers to be removed, dissolving the reaction products in the solution, while the thin film layers that do not react or react weakly with the solution remain intact. By alternately using different processing methods (ion etching, chemical solution etching, mechanical grinding), the multi-layer structure of the chip (Passivation, Metal, IDL) can be removed layer by layer. Through chip grinding and delayering, each layer of circuit wiring can be examined for defects, providing clear insights into the structure of each layer and technical support for subsequent analysis
Passivation Layer Removal
The passivation layer primarily consists of silicon nitride, which is dense and chemically stable, typically covering the outermost layer to protect the internal structure of the chip. It is usually removed using an ion etching machine. Under the drive of a radio frequency power supply, a voltage difference is created between the upper and lower electrodes, generating a glow discharge that ionizes the reactive gas into plasma. The free radicals in the plasma react with the material being etched, forming volatile compounds that are carried away by the airflow, thereby achieving anisotropic etching.
Metal Layer Removal and Dielectric Layer Removal
The metal layer is typically made of aluminum, with small amounts of silicon and copper elements mixed in. Diluted nitric acid, sulfuric acid, and hydrochloric acid can be used to remove the aluminum layer without corroding the surrounding dielectric layer.
The dielectric layer primarily consists of silicon dioxide and is generally composed of multiple film layers. Different layers are formed using various deposition methods, and some layers may be doped with other elements, resulting in varying removal rates for each film layer. Grinding methods can be employed for removal, requiring a high level of precision in the grinding process.
This operation is considered destructive analysis for the product, so special care must be taken to avoid introducing new damage during the analysis process. Therefore, there are high requirements for personnel experience, equipment capability, and environmental conditions.
In the early stages of IC structural analysis, optical microscopes (OM) were used to take photographs and observe IC circuit designs. However, as semiconductor manufacturing progresses to smaller processes in line with Moore's Law, moving from 28nm, 16nm, 10nm, 7nm, to 5nm and beyond, optical microscopes are limited to automatic photography with a magnification of only 1500x, making it difficult to clearly capture the circuit lines.
So, how can we clearly view micro-nano scale circuits? Scanning Electron Microscopes (SEM), which offer large-area scanning with magnifications up to 40,000x and localized imaging up to 1,000,000x, can be used for this purpose. SEM has two functions: One is for defect analysis, used to identify defects in products. In such cases, "localized imaging" is usually sufficient. The second function, which is the focus of this article, is for IC structural analysis. To avoid patent disputes and ensure patent avoidance, imaging cannot be limited to localized shots. Instead, extensive scanning and imaging are required to visualize all the circuits within the IC
During the delayering analysis, each layer removed requires the use of optical and electron microscopes to individually inspect for defects, including Via defects. Upon discovering anomalies, it is necessary to consider the overall condition of the sample and the nature of the defects to choose the best imaging method for presentation and further analysis. Currently, common integrated circuit products on the market are primarily divided into aluminum and copper processes (aluminum processes typically have 3-6 layers, with each layer 1-2 μm thick; copper processes typically have 3-10 layers, with each layer 0.1-0.2 μm thick). Different materials require different delayering methods.
